Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device

ABSTRACT

It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section  3  in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section  1,  in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section  4  as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section  4.  Further, the judgment signal JG is outputted as digital signal through an external terminal T 2  and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section  4.  Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom each of the prior Japanese Patent Application No. 2002-248134 filedon Aug. 28, 2002 and No. 2003-192151 filed on Jul. 4, 2003 the entirecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to adjustment of analog signaloutputted from an analog signal generating section of an internal powersource circuit or the like incorporated in a semiconductor integratedcircuit device, and more particularly to a semiconductor integratedcircuit device in which interface for input-output signals is achievedby digital signal and adjustment method of the semiconductor integratedcircuit device.

[0004] 2. Description of Related Art

[0005]FIG. 17 shows an internal power source circuit 300 incorporated ina semiconductor integrated circuit device, a fuse circuit 400 foradjusting the voltage of an internal power source voltage VII, and adecoding circuit 600 as circuit examples based on conventionaltechnology. The internal power source circuit 300 is constituted of anon-inverting amplification circuit employing an operational amplifiercircuit. If a gate voltage of a PMOS transistor MP1 is controlled by anoutput signal of the operational amplifier circuit, a reference voltageVREF inputted from a reference terminal REF, which is an inverting inputterminal, is subjected to non-inverting amplification so as to generatethe internal power source voltage VII. An amplification rate at thistime is determined by selecting resistance elements R, R0-R3 connectedto a path from the output terminal of the internal power source voltageVII to the non-inverting input terminal VAF of the operational amplifiercircuit. This selection is performed by supplying electricity to any oneof transfer gates S0-S3 connected between the respective resistanceelements R, R0-R3.

[0006] This selection is carried out by the decoding circuit 600. Thedecoding circuit 600 decodes predetermined signals FS<0>, <1> stored inthe fuse circuit 400 and selects any one of decoding signals D<0>-D<3>.Two-phase signals of in-phase and anti-phase for each of thepredetermined signals FS<0>, <1> are generated and logical add operationis executed by combining the respective signals so as to obtain thedecoding signal D<0>-<3>.

[0007] The fuse circuit 400 is constituted of a resistance element and afuse element and stores predetermined signals FS<0>,<1> for outputting apredetermined internal power source voltage VII. The fuse element is notcut out when a low level signal is stored and the fuse element is cutout when a high level signal is stored. In the semiconductor integratedcircuit, individual device characteristics vary because ofcharacteristic variation due to manufacturing reason and generally, thereference voltage VREF inputted to the reference terminal REF alsovaries. The predetermined signals FS<0>, <1> are signals for correctingthis variation so as to output the predetermined internal power sourcevoltage VII and is set up for each internal power source circuit 300.This setting work is called trimming work and carried out according to atest flow shown in FIG. 18.

[0008] In the test flow of FIG. 18, the internal power source voltageVII is measured with a tester device, which is an external device of thesemiconductor integrated circuit. Because the fuse element is not cutout at this stage, the predetermined signals FS<0>, <1> are low levelsignals. A transfer gate S0 is selected in the internal power sourcecircuit 300 so as to set up a minimum amplification rate. How theamplification rate of the internal power source circuit 300 should bechanged can be calculated preliminarily based on a measured voltagevalue of the internal power source voltage VII. That is, a fuse elementwhich should be cut out is predetermined depending on a differencebetween an initially measured voltage value of the internal power sourcevoltage VII and the predetermined value. FIG. 18 shows a test flow forbreaking a fuse element depending on the measured internal power sourcevoltage VII.

[0009] If the initially measured internal power source voltage VII is avoltage value VIIX lower than a range adjustable by selecting theamplification rate (VII<VIIX), the semiconductor integrated circuit is adefective product. If it is over the predetermined voltage value VIIZ(VII≧VIIZ), the fuse element does not have to be cut out. If respectivetransfer gates S1, S2 are selected, the initially measured voltagevalues VII, which is to be set as the predetermined voltage value VIIZ,are assumed to be VII1, VII2. Consequently, if the initially measuredvoltage value VII is VIIX, VII2, VII1, VIIZ, a fuse element which shouldbe cut out corresponding thereto is automatically determined.

[0010] According to a conventional technology, if the internal powersource voltage VII in the semiconductor integrated circuit incorporatingthe internal power source circuit 300 is trimmed, the internal powersource voltage VII needs to be measured according to a trimming testflow. Therefore, analog data which enables measurement of analog voltageneeds to be used for the trimming test. If other analog circuit than theinternal power source circuit 300 is loaded, the analog signal foradjustment needs to be also measured.

[0011] On the other hand, with intensification and miniaturization ofsemiconductor integrated circuit technology in recent years, thesemiconductor integrated circuit in digital field, which is representedby system LSI, has been loaded with an analog circuit block containinganalog function such as an internal power source circuit.

[0012] For the reason, the semiconductor integrated circuit, whichemploys digital signal as an input-output interface to an externalterminal, needs to be provided with a special measuring terminal (analogterminal) for adjusting the analog signal such as the internal powersource voltage, which is a problem to be solved.

[0013] More specifically, the analog circuit block, which is provided inthe semiconductor integrated circuit, is disposed at an arbitraryposition corresponding to semiconductor integrated circuit design. Wherethe analog terminal should be disposed differs depending on the design.A wiring path, wiring length, wiring load and the like from the analogcircuit block to the analog terminal differ depending on thesemiconductor integrated circuit design. In order to output an analogsignal to the analog terminal at a high precision, a sufficient careneeds to be taken to changes or the like of the analog value due tomixture of noise by digital signals from peripheral circuits block oradjacent wirings and wiring load on a wiring path for each design.Consequently, a great burden is applied to its design aspect in order toprovide with a special analog terminal necessary for adjustment of theanalog signal, which is a problem to be solved.

[0014] Further, with a test on the digital signal inputted/outputtedinto/from the digital terminal, an analog signal outputted from theanalog terminal needs to be measured. That is, both digital test andanalog test need to be carried out at the same time. Thus, it isnecessary to prepare a tester device having both digital testingfunction and analog testing function. Consequently, the tester devicebecomes complicated and expensive, so that testing time automaticallyincreases. Through-put from the test worsens and cost necessary for thetest increases, which are problems which should be solved.

[0015] Further, the digital test and analog test need to be carried outindependently and when the analog test is performed, the digitalfunction needs to be kept in a predetermined state. For the reason, aninfluence upon the analog signal by the operation of the digitalfunction cannot be tested, which is a problem to be solved.

SUMMARY OF THE INVENTION

[0016] The present invention has been made to solve at least one of theafore-mentioned problems that the prior art has had. It is an object ofthe present invention to provide a semiconductor integrated circuitdevice and an adjustment method of a semiconductor integrated circuitdevice capable of adjusting an analog signal without outputting theanalog signal to the external in a form of an analog value wherein ananalog signal to be adjusted is outputted from an analog signalgenerating section such as an internal power source circuit or the likebuilt in the semiconductor integrated circuit device.

[0017] To achieve the object, according to one aspect of the presentinvention, there is provided a semiconductor integrated circuit devicecomprising: an analog signal generating section for outputting an analogsignal; and a predetermined signal storing section for storing at leastone predetermined signal that is supplied to the analog signalgenerating section and sets the analog signal to a predetermined value,wherein digital signals are used for input/output interface to externalterminals, for adjusting the analog signal, the semiconductor integratedcircuit device further comprises a judgment section for outputting atleast one judgment signal that corresponds to a comparison result of theanalog signal corresponding to at least one adjustment signal and thepredetermined value generated based on power source voltage, for eachadjustment signal supplied to the analog signal generating section inaccordance with a test signal, and in case the judgment signal judgesthat the analog signal has the predetermined value, the adjustmentsignal corresponding to the as-judged analog signal is stored in thepredetermined signal storing section as the predetermined signal.

[0018] In the semiconductor integrated circuit device directed to theone aspect of the present invention, when an analog signal is adjustedfor the analog signal generating section build in a semiconductorintegrated circuit device wherein digital signals are used forinput/output interface to external terminals, at least one adjustmentsignal is supplied for generating an analog signal. The judgment sectioncompares the generated analog signal with the predetermined valuegenerated based on power source and output the comparison result in aform of at least one judgment signal. The predetermined signal storingsection stores an adjustment signal that adjusts an analog value to apredetermined value in accordance with at least one judgment signal in aform of a predetermined signal.

[0019] Furthermore, there is provided an adjustment method of thesemiconductor integrate circuit device, directed to the one aspect ofthe present invention, there is provided an adjustment method of asemiconductor integrated circuit device that generates an analog signalhaving a predetermined value based on at least one predetermined signalstored and uses digital signals for input/output interface to externalterminals, for adjusting the analog signal, the adjustment methodcomprising the steps of: a signal generating step for generating theanalog signal that corresponds to at least one adjustment signal; ajudgment step for judging a comparison result of the analog signalgenerated and the predetermined value generated based on power sourcevoltage, the judgment step being executed inside the semiconductorintegrated circuit device; and a storing step for storing the adjustmentsignal as the predetermined signal in case the analog signal is judgedas having the predetermined value through the judgment step.

[0020] In the adjustment method of the semiconductor integrated circuitdevice directed to the one aspect of the present invention, when ananalog signal is adjusted for the analog signal generating section buildin a semiconductor integrated circuit device wherein digital signals areused for input/output interface to external terminals, an analog signalcorresponding to at least one adjustment signal is generated in thesignal generating step, and in the judgment step, an analog signalgenerated and the predetermined value generated based on power sourcevoltage are compared inside the semiconductor integrated circuit device.In the storing step, at least one adjustment signal is stored as atleast one predetermined signal in case the analog signal is judged ashaving the predetermined value.

[0021] Since the judgment section or the judgment step is provided, ananalog signal outputted for each adjustment signal and the predeterminedvalue can be compared. Thereby, judgment of analog signal can beexecuted inside the semiconductor integrated circuit device.

[0022] That is, it is not necessary to output an analog signal to theexternal terminal of the semiconductor integrated circuit device.Furthermore, it is not necessary to arrange an output dedicated externalterminal for an analog signal and wiring for an analog signal to theoutput dedicated external. Thereby, consideration for analog wiring isnot necessitated and this contributes to simplification of designprocess of an semiconductor integrated circuit device.

[0023] Furthermore, since an analog signal is not outputted from theexternal terminal, a test for an analog signal is not required. That is,there may be arranged a tester device having digital function for adigital-interface-type external terminal. It is not necessary to providea complicated tester device that has both digital function and analogfunction. Furthermore, the inventive semiconductor integrated circuitdevice does not require system to switch test condition between digitalfunction and analog function, whereby overhead of test time due toswitching operation. Reduce of test cost thus can be realized.

[0024] It should be noted that the predetermined value herein is a valuefor a comparison judgment of an analog signal as well as an analogvalue. The predetermined value can be generated based on power sourcevoltage that is supplied to the semiconductor integrated circuit deviceat the time of adjustment test. Once power source voltage is set as thepredetermined voltage value for adjustment test, it is not necessary toinput a predetermined analog value from an external terminal aspredetermined value. A predetermined value can be generated byappropriately lowering/dividing power source voltage or appropriatelycombining those resultant voltages.

[0025] Furthermore, it is preferable that the predetermined value is apredetermined analog value region between a first comparison referencevalue and a second comparison reference value and the judgment signaljudges which analog value region sectioned by two or more comparisonreference values including the first and the second comparison referencevalues the analog signal exists in. Thereby, fluctuation of the analogsignal from the predetermined value can be grasped and depending onjudgment result, at least one adjustment signal can be fluctuated tomake the analog signal approximate the predetermined value immediately.

[0026] It is preferable that the judgment section includes a pluralityof comparing sections for comparing the analog signal with each of thetwo or more comparison reference values, and an encoding section foroutputting encoding signals in a manner of receiving output signals fromthe plurality of comparing sections and discriminating the analog valueregion where the analog signal exists. As encoding signals, the encodingsection may output digital signals that have a minimum essential numberof bits being enough to discriminate analog value regions.

[0027] Furthermore, according to another aspect of the presentinvention, there is provided a semiconductor integrated circuit devicecomprising: an analog signal generating section for outputting an analogsignal; and a predetermined signal storing section for storing at leastone predetermined signal that is supplied to the analog signalgenerating section and sets the analog signal to a predetermined value,wherein digital signals are used for input/output interface to externalterminals, and the semiconductor integrated circuit device furthercomprises virtual load section for varying load against the analogsignal in response to a load setting signal to be supplied. Stillfurther, there is provided an adjustment method of the semiconductorintegrate circuit device, directed to the another aspect of the presentinvention, there is provided an adjustment method of a semiconductorintegrated circuit device that generates an analog signal having apredetermined value based on at least one predetermined signal storedand uses digital signals for input/output interface to externalterminals, the adjustment method adjusting the analog signal through avirtual load step for varying load against the analog signal inaccordance with a load setting signal. Since there is provided thevirtual load section or the virtual load step, virtual load can beconnected appropriately. Various operation states inside a semiconductorintegrated circuit device such as digital function and other analogfunction can be reproduced like a simulation. This adjustment method maybe applied to a test for analog signal adjustment so that analog signaladjustment can be conducted under load condition close to actualoperation.

[0028] The above and further objects and novel features of the inventionwill more fully appear from the following detailed description when thesame is read in connection with the accompanying drawings. It is to beexpressly understood, however, that the drawings are for the purpose ofillustration only and are not intended as a definition of the limits ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a first principle diagram of the present invention;

[0030]FIG. 2 is a second principle diagram of the present invention;

[0031]FIG. 3 is a circuit block diagram of a first embodiment;

[0032]FIG. 4 is a circuit diagram of a specific example directed to thefirst embodiment;

[0033]FIG. 5 shows operational waveform of the specific example directedto the first embodiment;

[0034]FIG. 6 is a trimming test flow of the first embodiment;

[0035]FIG. 7 is a circuit diagram of a variant of a judgment section;

[0036]FIG. 8 is a circuit block diagram of a second embodiment;

[0037]FIG. 9 is a circuit diagram of a specific example directed to thesecond embodiment;

[0038]FIG. 10 shows operational waveform of the specific exampledirected to the second embodiment;

[0039]FIG. 11 is a trimming test flow of the second embodiment;

[0040]FIG. 12 is a circuit block diagram of a third embodiment;

[0041]FIG. 13 is a circuit diagram of a specific example directed to thethird embodiment;

[0042]FIG. 14 is a circuit diagram of a first specific example directedto a fourth embodiment;

[0043]FIG. 15 is a circuit diagram of a second specific example directedto the fourth embodiment;

[0044]FIG. 16 shows operational waveform obtained incase multiplejudgment is made;

[0045]FIG. 17 is a circuit diagram of prior art; and

[0046]FIG. 18 is a conventional trimming test flow.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047]FIG. 1 shows a first principle diagram of the present invention.An analog signal AOUT is outputted from an analog signal generatingsection 3 in which an adjustment signal AD is inputted. If theadjustment signal AD is digital signal, the analog signal AOUT isoutputted from the digital signal by the analog signal generatingsection 3 and input-output signal is subjected to D/A conversion by theanalog signal generating section 3. If the adjustment signal AD isdigital signal, the adjustment signal AD may be inputted from anexternal terminal T1. Contrary to this, an analog signal AOUT is asignal used in the semiconductor integrated circuit device and neveroutputted as an analog signal from an external terminal.

[0048] The analog signal AOUT is inputted to a judgment section 1 andcompared with a predetermined value for judgment. The predeterminedvalue is a reference value for comparison and judgment and needs to bekept at a predetermined fixed value. A judgment section 1 generates ajudgment signal based on the power source voltage VDD supplied to anexternal terminal T3. In a test operation including adjustment of theanalog signal, the power source voltage VDD supplied to thesemiconductor integrated circuit device can be kept at a predeterminedvoltage value when it is supplied. Therefore, the predetermined valuecan be generated based on the power source voltage VDD supplied to theexternal terminal T3. The power source voltage VDD needs to be alwayssupplied so as to operate the semiconductor integrated circuit device.By using the power source voltage VDD, the predetermined value can begenerated without supplying any analog signal from the externalterminal.

[0049] The judgment signal JG is outputted from the judgment section 1.This judgment signal JG may be made to act on a predetermined signalstoring section 4 as an internal signal of the semiconductor integratedcircuit device and further, may be outputted through an externalterminal T2. If the judgment signal JG is made to act on thepredetermined signal storing section 4, the adjustment signal AD isfetched into the predetermined signal storing section 4 based on thejudgment signal JG. If the judgment signal is outputted from theexternal terminal T2, the judgment signal JG is digital signal. Anoutputted judgment signal JG is inputted to a control section (notshown) outside such as a tester device. The external control sectionacquires the adjustment signal AD at this time based on the judgmentsignal JG and terminates the adjustment test operation at the same time.Then, the external control section stores an acquired adjustment signalas a predetermined signal prior to or after the termination of theadjustment test operation. If a digital signal JG is outputtedcorresponding to the analog signal AOUT to be inputted to the judgmentsection 1, the input-output signal is subjected to A/D conversion at thejudgment section 1.

[0050] The predetermined signal storing section 4 can be constituted ofelectrically rewritable memory elements regardless of volatile ornonvolatile, by a circuit structure having data holding function such asa register, flip-flop. Further, a fuse element, a 1-time ROM or the likewhich enables write of only a single time may be used. The fuse elementmay be cut out electrically in addition to cutting with laser radiationor the like. Here, the electric processing may be controlled within thesemiconductor integrated circuit device or by any external controlsection.

[0051]FIG. 2 shows a second principle diagram of the present invention.The analog signal generating section 3 outputs an analog signal AOUTcorresponding to the adjustment signal AD. A virtual load section 2 isconnected to the analog signal AOUT. The virtual load section 2 canchange a load connected to the analog signal AOUT under a control by theload setting signal LDS. If the load setting signal LDS is set upappropriately, a similar load to a load applied to the analog signal ADcan be connected falsely under each operation state of the semiconductorintegrated circuit device. If the load setting signal LDS is set up whenthe analog signal AOUT is adjusted according to the adjustment signalAD, the analog signal AOUT can be judged by connecting a similar load toactual operation without actuating the semiconductor integrated circuitdevice.

[0052] Here, it may be so constructed that the adjustment signal AD andthe load setting signal LDS is generated within the semiconductorintegrated circuit device or inputted from outside through the externalterminal T1, T4. If the adjustment signal AD and the load setting signalLDS are inputted from outside through the external terminal T1, T4,these signals are digital signals.

[0053] Hereinafter, the first to fourth embodiments of the semiconductorintegrated circuit device and adjustment method of the semiconductorintegrated circuit device of the present invention will be described indetail with reference to drawings of FIGS. 3-16. The first to fourthembodiments adopt such a circuit structure in which an internal powersource circuit 31 is provided as the analog signal generating section 3and the internal power source voltage VII is outputted as the analogsignal AOUT.

[0054]FIG. 3 shows a circuit block diagram of the first embodiment foradjustment of the internal power source voltage VII. An adjustmentsignal EAD<m:0> to be inputted from an external terminal T11 is inputtedto one input terminal of a multiplexer 51. A predetermined signalFS<m:0>, which is to be stored in a fuse circuit (or memory circuit) 41,is inputted to the other input terminal of the multiplexer 51. Themultiplexer 51 is controlled by a test signal TS inputted to theexternal terminal T15. In adjustment test for the internal power sourcevoltage VII, the adjustment signal EAD<m:0> is selected. In a normalstate after the adjustment signal is stored in the fuse circuit (ormemory circuit) 41 after the adjustment test is completed, thepredetermined signal FS<m:0> is selected. The selected signal EAD<m:0>or FS<m:0> is decoded by a decoding circuit 61. A decoding signal D<n:0>outputted from the decoding circuit 61 is inputted to the internal powersource circuit 31.

[0055] The internal power source voltage VII outputted from the internalpower source circuit 31 is inputted to a comparing section 12 in thejudgment section 11. Further, the power source voltage VDD supplied tothe external terminal T13 is inputted to the comparing section 12. Thecomparing section 12 sets up a predetermined value based on the powersource voltage VDD. A comparison result signal J from the comparingsection 12 is inputted to the encoding section 13. Then, the encodingsection 13 judges a comparison result and the judgment signal JG isoutputted.

[0056] For storage of the adjustment signal EAD<m:0> to the fuse circuit(or memory circuit) 41, a case where it is controlled within thesemiconductor integrated circuit device and a case where it iscontrolled by an external control device (not shown) such as a testerdevice can be considered. If it is controlled internally, the judgmentsignal JG is inputted to the fuse circuit (or memory circuit) 41 as acontrol signal and by blowing of the fuse element based on the judgmentsignal JG or writing operation into the memory element, the adjustmentsignal EAD<m:0> is fetched in. If it is controlled from outside, thejudgment signal JG is digital signal and outputted from the externalterminal T12. By blowing of the fuse element from outside or writingoperation into the memory element based on the outputted judgment signalJG, the adjustment signal EAD<m:0> is stored. When it is also controlledinternally, it is permissible to output the judgment signal JG from theexternal terminal T12 as digital signal. In this case, it is possible tonotify of completion of the adjustment test operation with the judgmentsignal JG and stop supply of the test signal TS and adjustment signalEAD<m:0>.

[0057] If the test signal TS inputted from the external terminal T15 isactivated, the adjustment signal EAD<m:0> is inputted from the externalterminal T11 every predetermined cycle. The inputted adjustment signalEAD<m:0> is decoded to a decoding signal D<n:0> by the decoding circuit61 through the multiplexer 51 and inputted to the internal power sourcecircuit 31. The internal power source circuit 31 outputs the internalpower source voltage VII corresponding to the decoding signal D<n:0>.The outputted internal power source voltage VII is inputted to thecomparing section 12 in the judgment section 11 and compared with apredetermined value generated based on the power source voltage VDD. Thecomparison result signal J is inputted to the encoding section 13. Theencoding section 13 judges a comparison result so as to output thejudgment signal JG. If it is judged that the judgment signal JG does notcoincide with the predetermined value of the internal power sourcevoltage VII, the adjustment signal EAD<m:0> is updated after apredetermined cycle and inputted and then, the comparison judgmentoperation is repeated. If it is judged that the judgment signal JGcoincides with the predetermined value of the internal power sourcevoltage VII, the adjustment signal EAD<m:0> produced as a result of thejudgment on that coincidence is stored in the fuse circuit (or memorycircuit) 41 by internal control or external control depending on settingof the semiconductor integrated circuit device.

[0058]FIG. 4 shows a specific circuit diagram of the first embodiment.This Figure indicates that 2-bit signal (m=1) is inputted from theexternal terminals T11A, T11B as the adjustment signal EAD <1:0>. Thefuse circuit 41A stores the predetermined signal FS<1:0> at a connectionpoint between a resistance element connected to the power source voltageand the fuse element F<1:0> connected to the ground voltage. If the fuseelement F<1:0> is not cut out, a low level signal is stored and if it iscut out, a high level signal is stored.

[0059] The multiplexer 51A selects either one of the adjustment signalEAD<1:0> and the predetermined signal FS<1:0>. Transfer gates SE0, SE1and SF0, SF1 are provided between each signal path and the outputterminal. Each transfer gate is supplied with electricity and controlledby a test signal TS inputted from the external terminal T15A. Thetransfer gates SE0, SE1 and the transfer gates SF0, SF1 are controlledexclusively from each other because the connecting relations of thetransfer gates SE0, SE1 and the transfer gates SF0, SF1 are reverse toeach other. The transfer gates SE0, SE1 are supplied with electricity bya low level signal of the test signal TS so that the predeterminedsignal EAD <1:0> is selected. The transfer gate SF0, SF1 are suppliedwith electricity by a high level signal of the test signal TS so thatthe predetermined signal FS<1:0> is selected. The adjustment testoperation for the internal power source voltage VII is carried out by alow level signal of the test signal TS.

[0060] The two-bit signals selected by the multiplexer 51A are inputtedto the decoding circuit 61A. After that signals are inputted, signals ofthe in-phase and anti-phase are generated for each bit. Four types ofdecoding are carried out corresponding to combinations of the respectivesignals. That is, if the adjustment signals EAD<1:0> are taken as anexample, decoding signals D<0>-D<3> are selected successively to(EAD<1>, EAD<0>)=(0, 0), (0, 1), (1, 0), (1, 1) by NOR-gate NOR0-NOR3 soas to produce high level signals.

[0061] The internal power source circuit 31A outputs the internal powersource voltage VII from a connection point between the PMOS transistorMP1 and the resistance element array of R, R0-R3. The gate terminal ofthe PMOS transistor MP1 is controlled by an operation amplifier. Thereference voltage VREF is inputted to a reverse-input terminal of theoperation amplifier from the reference terminal REF. A feedback loop isconstructed between the non-inverting input terminal and the outputterminal of the internal power source voltage VII. A fed-back feedbackvoltage VAF is inputted to the non-inverting input terminal. Thetransfer gates S0-S3 for connecting between each connection point of theresistance element array of R, R0-R3 and the non-inverting inputterminal are selected corresponding to the decoding signals D<0>-D<3> soas to form a feedback loop. The internal power source circuit 31A is anon-inverting amplification circuit having a predetermined amplificationrate which is determined by a feedback position in the resistanceelement array of R, R0-R3.

[0062] In this feedback loop, depending on switching of the decodingsignals D<0>-D<3> accompanied by switching of the adjustment signalsEAD<1:0>, each of the transfer gates S0-S3 is turned ON successively.The feedback positions in the resistance element array of R, R0-R3 areshifted to low voltage side successively so as to increase theamplification rate. The internal power source voltage VII is raisedsuccessively so as to obtain an output voltage value.

[0063] The internal power source voltage VII is inputted to thecomparing section 12A. The comparing section 12A contains twocomparators C0, C1. Reference voltages VII0, VII1 of the respectivecomparators C0, C1 are obtained by dividing the power source voltage VDDinputted from the external terminal T13A with resistance elementsRC0-RC2. Here, a voltage value region between the reference voltage VII0and VII1 is a predetermined value. If the internal power source voltageVII is inputted to each of the comparators C0, C1, comparison of voltagewith the predetermined value is carried out. If the internal powersource voltage VII is in a lower voltage value region than VII0 and ifin a higher voltage value region than VII1, the comparison signals J<0>,J<1> outputted from each of the comparators C0, C1 are of the in-phase.If the comparison signals are in a voltage value region between thereference voltages VII0 and VII1, the comparison signals J<0>, J<1> areof anti-phase.

[0064] The encoding section 13A, which encodes the comparison signalsJ<0>, J<1> so as to output the judgment signal JG, inverts thecomparison signal J<0> logically and acquires NOR logic between thecomparison signal J<1> and J(C). If the internal power source voltageexists in a voltage value region between the reference voltages VII0 andVII1 as described above, the comparison signals J<0>, J<1> are of theanti-phase and input signals to the NOR gate become low level.Therefore, in this case, a high level signal is outputted as thejudgment signal JG and it is determined that the internal power sourcevoltage VII is a predetermined value. Because the judgment signal JGoutputted from the encoding section 13A is digital signal, it can beoutputted from a external terminal T12A. The judgment section isconstituted of the comparing section 12A and the encoding section 13A.

[0065]FIG. 5 shows an operation waveform in a specific example of thefirst embodiment. If the test signal TS is inverted to low level, theadjustment test on the internal power source voltage VII is started.With this state, the adjustment signals EAD <1:0> are incrementedsuccessively from a logical level of (0, 0). Because the adjustmentsignals EAD<1:0> are selected by the multiplexer 51A corresponding tothe test signal TS, each of the decoding signals D<0>-D<3> is selectedsuccessively to produce high level signal. The amplification rate of theinternal power source circuit 31A is increased corresponding toselection of the decoding signals D<0>-D<3>. Therefore, the internalpower source voltage VII is increased successively.

[0066] Because the internal power source voltage VII is smaller than thereference voltage VII0 of the comparing section 12A when the decodingsignal D<0> and D<1> is selected, the comparison signals J<0>, J<1> areof high level. Because the internal power source voltage VII is largerthan the reference voltage VII1 of the comparing section 12A when thedecoding signal D<3> is selected, the comparison signals J<0>, J<1> areof low level. In either case, one input terminal of the NOR gate of theencoding section 13A becomes high level. Therefore, the judgment signalJG keeps low level.

[0067] When the decoding signal D<2> is selected, the internal powersource voltage VII is located between the reference voltages VII0 andVII1 of the comparing section 12A. Thus, the comparison signal J<0> isof high level while the J<1> is low level. The input terminals of theNOR gate of the encoding section 13A become low level. Therefore, thejudgment signal JG becomes high level.

[0068] The adjustment signals EAD<1:0> at this time are memorized in anexternal control section by the judgment signal JG outputted from theexternal terminal T12A. After the test signal TS is inverted to highlevel and the adjustment test is terminated, a predetermined fuseelement in a fuse circuit 41A is cut out. More specifically, the fuseelement F<1> is cut out in order to store the adjustment signals(EAD<1>, EAD<0>)=(1, 0). Consequently, the adjustment signals (EAD<1>,EAD<0>)=(1, 0) are stored in the fuse circuit 41A as the predeterminedsignals (FS<1>, FS<0>)=(1, 0).

[0069]FIG. 6 shows a test flow for a case where a predetermined signalsFS<m:0> are stored by executing a trimming test on the internal powersource voltage VII using a tester device as an external control section.A portion surrounded by the parentheses in FIG. 6 indicates processingwithin the semiconductor integrated circuit device.

[0070] Test mode is set up in a tester device when the trimming test isstarted (S1). Consequently, the test signal TS is inverted to low leveland at the same time, the power source voltage VDD is fixed to apredetermined voltage value. Further, it is initialized to theadjustment signals EAD<m:0>=0. With this state, the adjustment signalsEAD<m:0> are supplied successively to the external terminal of thesemiconductor integrated circuit device. The adjustment signals EAD<m:0>are decoded in the semiconductor integrated circuit device so as tooutput one of decoding signals D<n:0> and correspondingly, the internalpower source voltage VII is outputted. The outputted internal powersource voltage VII is compared for judgment (S2).

[0071] As a result of the judgment, the judgment signal JG, which isdigital signal outputted from the external terminal, is judged (S3). Ifa low level is maintained (S3: NO), it means that the internal powersource voltage VII is not a predetermined value. Therefore, theadjustment signals EAD<m:0> are incremented by one and updated (S4). Ifthe incremented adjustment signals EAD<m:0>are not zero which is aninitial value (S5: NO), a new adjustment signals EAD<m:0> is supplied tothe external terminal and the processing after S2 is repeated. If theupdated adjustment signals EAD<m:0> return to the initial value 0 (S5:YES), it means that in this semiconductor integrated circuit device, itsinternal power source voltage VII cannot be adjusted to thepredetermined value and then it is determined that this is a defectiveproduct (S6).

[0072] If the judgment signal JG turns to a high level as a result ofthe judgment (S3: YES), it means that the internal power source voltageVII is a predetermined value. The value of the adjustment signalsEAD<m:0> at this time are acquired as storage data into the fuse circuit(or memory circuit) 41 (S7). Based on this acquired data, theappropriate fuse elements are cut out (or the adjustment signalsEAD<m:0> are fetched in).

[0073]FIG. 7 shows a modification of the judgment section. The comparingsection 12B adds resistance elements RC3, RC4 and comparators C2, C3 tothe comparing section 12A (see FIG. 4). The reference voltages of therespective comparators C0-C3 are reference voltages VII0, VII1, VII2,VII3 respectively. The reference voltages VII0-VII3 are obtained bydividing the power source voltage VDD inputted from the externalterminal by resistance elements RC0-RC4. If the voltage value regionbetween the reference voltages VII1 and VII2 is set to a predeterminedvalue, two voltage value regions exist each up and down. Five voltagevalue regions can be identified.

[0074] The comparing section 12B identifies in which voltage valueregion of those five regions the internal power source voltage VIIexists. This identification is carried out when the comparison signalsJ<3:0> outputted from the respective comparators C0-C3 are set to “1”successively from the comparison signal J<0> to the comparison signalJ<3>. The encoding section 13B encodes the comparison signals J<3:0> soas to output 3-bit judgment signals JG<2:0>. In an encoding table ofFIG. 7, the judgment signals JG<2:0> are incremented as the comparisonsignals J<3:0> are increased. If the internal power source voltage VIIexists in a predetermined voltage value region, (0, 0, 1, 1) is obtainedas the comparison signals J<3:0>. At this time, (0, 1, 0) are outputtedas the judgment signals JG<2:0>.

[0075] The judgment signals JG<2:0> have information about in whichvoltage value region the internal power source voltage VII exists if itexists in other voltage value region than the predetermined voltagevalue region. Thus, the voltage value region of the internal powersource voltage VII can be grasped with the judgment signals JG<2:0>, sothat transition of the adjustment signals can be brought near thepredetermined signal more securely and rapidly. Although an example inwhich the judgment signals are 3-bit signals has been described in FIG.7, this signal may be composed of more bits. Consequently, a moreaccurate voltage value region of the internal power source voltage VIIcan be grasped, so that the adjustment signals can be brought near thepredetermined signals more rapidly.

[0076]FIG. 8 shows a circuit block diagram of the second embodimentabout adjustment of the internal power source voltage VII. This circuithas a memory circuit (or fuse circuit) 42 instead of the fuse circuit(or memory circuit) 41 of the first embodiment (FIG. 3). Additionally,an adjustment signal generating section 71 is incorporated.

[0077] The adjustment signal generating section 71 comprises anoscillation circuit 72 and a counter circuit 73 in which an oscillationsignal CLK from an oscillation circuit 72 is inputted. Further, theoscillation circuit 72 and the counter circuit 73 are controlled by thetest signal TS inputted to the external terminal T15. The countercircuit 73 counts the oscillation signal CLK and outputs adjustmentsignals CAD<m:0> at every predetermined timing. Here, in order to countthe predetermined timing, preferably, the oscillation signal CLK isdivided or increment timing of the counter circuit 73 is subjected toadjustment or the like appropriately. Consequently, the adjustmentsignals CAD<m:0> are generated in the semiconductor integrated circuitdevice and therefore, the external terminals T11 (FIG. 3) for use forinput of the adjustment signals EAD<m:0> are not required. As a result,the quantity of the external terminals for adjustment and test for theinternal power source voltage VII can be reduced.

[0078] Storage of the adjustment signals CAD<m:0> into the memorycircuit (or fuse circuit) 42 is controlled within the semiconductorintegrated circuit device. The judgment signal JG is inputted to thememory circuit (or fuse circuit) 42 as a control signal and by writingoperation into a memory element based on the judgment signal JG or bycutting of the fuse element, the adjustment signals CAD<m:0> are fetchedin. In this case, the cutting of the fuses is performed by applying anelectric stress. The stored signals are supplied as predeterminedsignals MS<m:0> at the time of normal operation.

[0079] In the meantime, although the judgment signal JG of this case isa signal for internal control, this signal may be outputted from anexternal terminal as digital signal. It is also possible to notify ofcompletion of the adjustment test operation with the judgment signal JGand stop supply of the test signal TS from a tester circuit or the like.

[0080]FIG. 9 shows a major component circuit diagram according to aspecific example of the second embodiment. This indicates a case where a2-bit signals (m=1) are outputted as adjustment signals CAD <m:0> fromthe counter circuit 73A. In the oscillation circuit 72A, the test signalTS inputted from the external terminal T15A is inputted to an inputterminal of the NAND gate as an enable signal. That is, the NAND gate isturned to logical inverting gate by the test signal TS and constitutes aring oscillator together with an inverter gate array connected to theother input terminal.

[0081] The counter circuit 73A is a counter circuit in which flip-flopis cascade-connected. The oscillation signal CLK is inputted to a clockterminal (CLK) of the flip-flop of the lowest bit. Then, the adjustmentsignals CAD<1:0> are outputted from each flip-flop. The adjustmentsignals CAD<1:0> are supplied to the multiplexer 51 and at the same timeto the memory circuit 42A.

[0082] The memory circuit 42A contains latch sections L0, L1 for eachbit of the adjustment signals CAD<1:0> as a memory cell. The inputtedadjustment signals CAD<1:0> are connected to the latch sections L0, L1through the transfer gates SC0, SC1. The transfer gates SC0, SC1 areturned ON and controlled depending on a result of logical productoperation between the oscillation signal CLK and the judgment signal JG.More specifically, when it is determined that the internal power sourcevoltage VII is a predetermined value by the adjustment signals CAD<1:0>updated depending on the output of the oscillation signal CLK, a highlevel signal is outputted as the judgment signal JG. The transfer gatesSC0, SC1 are turned ON by a logical product between the high-leveljudgment signal JG and the high level period of the oscillation signalCLK, so that the adjustment signals CAD<1:0> are stored in the latchsections L0, L1 of the memory circuit 42A. The adjustment signalsCAD<1:0> stored in the latch section are supplied to the multiplexer 51as the predetermined signals MS<1:0>.

[0083] Because a circuit structure not described in FIG. 9 of thespecific example of the second embodiment is the same as the circuitstructure of the specific example of the first embodiment (FIG. 4),description thereof is omitted. In this case, inverted signal of thetest signal TS is inputted to the multiplexer.

[0084]FIG. 10 shows an operation waveform according to a specificexample of the second embodiment. If the test signal TS is inverted to ahigh level, adjustment test is started. The adjustment signals CAD<1:0>outputted from the counter circuit 73A at every cycle of the oscillationsignal CLK are incremented. Such an operation that the decoding signalsD<0>-D<3> are selected successively depending on the adjustment signalsCAD<1:0> and the internal power source voltage VII is switched so as tooutput the comparison signals J<1:0> and the judgment signal JG is thesame as the specific example of the first embodiment (FIG. 5). Accordingto a specific example of the second embodiment, the adjustment signalsCAD<1:0> are written into the memory circuit 42A based on transition ofthe judgment signal JG to a high level. The written adjustment signalsCAD<1:0> are stored as the predetermined signals MS<1:0>.

[0085] According to the specific example of the second embodiment, whenthe judgment signal JG turns to a high level during the operation of theadjustment test with the test signal TS kept at a high level, thestorage operation of the adjustment signals CAD<1:0> into the memorycircuit 42A is carried out. FIG. 10 indicates a case where increment ofthe adjustment signals CAD<1:0> are continued after the adjustmentsignals CAD<1:0> are stored into the memory circuit 42A, so that theadjustment test is continued. It is permissible to construct that whenthe storage operation is completed, the test signal TS is transferred toa low level by outputting the judgment signal JG as digital signal fromthe external terminal T12A so as to terminate the adjustment test.

[0086]FIG. 11 shows a test flow of a case where trimming test is carriedout for the internal power source voltage VII using an external testerdevice so as to store the predetermined signals MS<m:0>. A portionsurrounded by the parentheses indicates processing within thesemiconductor integrated circuit device.

[0087] After the trimming test is started, test mode is set up in thetester device (S11). Consequently, the test signal TS is inverted to ahigh level and the power source voltage VDD is fixed to a predeterminedvoltage value. In the semiconductor integrated circuit device whichreceives a high-level test signal TS, the counter circuit is reset sothat the adjustment signals CAD<1:0> are initialized (S12). After that,the adjustment signals CAD<1:0> which are output signals from thecounter circuit is decoded by a decoding signals D<n:0> and then, theinternal power source voltage VII is outputted. Further, comparison withthe predetermined value and judgment is carried out (S13).

[0088] If the judgment signal JG which is digital signal outputted fromthe external terminal keeps low level as a result of judgment (S14: NO),unless time-out is reached after time-out of the adjustment test isdetected (S15: NO), comparison and judgment about the internal powersource voltage VII accompanying increment operation of the adjustmentsignals CAD<1:0> within the semiconductor integrated circuit device arecontinued. If the time-out is reached (S15: YES), it is determined thatthis semiconductor integrated circuit device is a defective product(S16).

[0089] If the judgment signal JG turns to a high level as a result ofthe judgment (S14: YES), the adjustment signals CAD<1:0> are stored asmemory data in the semiconductor integrated circuit device (S17). Thestored data is the predetermined signals MS<1:0>. At this time, thetester device may invert the test signal TS to a low level and terminatethe adjustment test.

[0090] A circuit block diagram of the third embodiment for adjustment ofthe internal power source voltage VII shown in FIG. 12 indicates a casewhere the adjustment test of the internal power source voltage VII inthe semiconductor integrated circuit device provided with aself-diagnosis test (BIST) circuit 81 is executed as a self-diagnosistest by BIST circuit 81.

[0091] Additionally, this block diagram shows a case where thepredetermined signals MS<m:0> are stored in a nonvolatile memory circuit43. Because generally, data writing time to the nonvolatile memorycircuit 43 is longer than increment period of the adjustment signalBAD<m:0>, this embodiment includes a latch circuit 44 for temporarilyholding the adjustment signals BAD<m:0> to be stored. The adjustmentsignals BAD<m:0> are held on the latch circuit 44 and written into thenonvolatile memory circuit 43.

[0092] The BIST circuit 81 starts the self-diagnosis test according tothe test signal TS supplied from the external terminal T15. For theadjustment test of the internal power source voltage VII, an adjustmenttest signal TSAD is outputted to the multiplexer 51. At the same time,the adjustment signals BAD<m:0> are transferred and outputted at everypredetermined cycle. The predetermined timing mentioned here refers to atime longer than a time taken until the internal power source voltageVII is updated by the internal power source circuit 31 and theadjustment signals BAD<m:0> are fetched into the latch circuit 44corresponding to the judgment signal JG, this time also including a timefor outputting a judgment result as the judgment signal JG by thejudgment section 11.

[0093] The judgment signal JG outputted from the judgment section 11 isinputted to the latch circuit 44 and functions as a latch signal and atthe same time, is inputted to the BIST circuit 81. When the judgmentsignal JG indicating that the internal power source voltage VII turns tobe a predetermined value is inputted, the adjustment signals BAD<m:0> atthis time are fetched into the latch circuit 44 and the program signalPGM is outputted from the BIST circuit 81 into the nonvolatile memorycircuit 43. The adjustment signals BAD<m:0> latched to the latch circuit44 based on the program signal PGM are written into the nonvolatilememory circuit 43. At the same time, transition of the adjustmentsignals BAD<m:0> outputted from the BIST circuit 81 is stopped.

[0094]FIG. 13 shows a major component circuit diagram according to aspecific example of the third embodiment. This Figure indicates a casewhere 2-bit signals (m=1) are outputted as the adjustment signalsBAD<m:0> from the BIST circuit 81. The adjustment signals BAD<1:0>outputted from the BIST circuit 81 are supplied to the multiplexer 51and at the same time to the latch circuit 44A.

[0095] The latch circuit 44A has the same structure as the memorycircuit 42A (FIG. 9). A latch section is provided for each bit of theadjustment signals BAD<1:0> and the inputted adjustment signals BAD<1:0>are connected to the latch section through transfer gate. The transfergate is turned ON and controlled depending on the judgment signal JG.That is, the adjustment signal BAD<1:0> are fetched into the latchsection because the transfer gate is turned ON by the judgment signal JGof a high level when it is determined that the internal power sourcevoltage VII is a predetermined value. The adjustment signals BAD<1:0>fetched into the latch section is written into a nonvolatile memory cellthrough a write circuit of the nonvolatile memory cell based on aprogram signal PGM.

[0096] Because the circuit structure not indicated in FIG. 13 of thespecific example of the third embodiment is the same as the circuitstructure of the specific example (FIG. 4) of the first embodiment,description of that section is omitted.

[0097]FIG. 14 shows a circuit diagram indicating a first specificexample of the fourth embodiment of a virtual load section. A PMOStransistor MP2 is provided as the virtual load section 24A between theinternal power source voltage VII and the ground voltage. A load signalgenerating section 94A is provided to supply a load signal VG to a gateterminal of the PMOS transistor MP2.

[0098] In the load signal generating section 94A, the PMOS transistorMP3 and resistance element array are connected in series between thepower source voltage VDD and the ground voltage. A load signal VG isoutputted from each connection point of the resistance element arraythrough each transfer gate. An inverted signal of the test signal TS isinputted to the gate terminal of the PMOS transistor MP3 through aninverter gate. A load setting signals LDS<i:0> are inputted as a digitalsignal from external terminals T46A. The inputted load setting signalsLDS<i:0> are decoded by a decoding circuit and selects a transfer gateprovided at each connection point of the resistance element array andturns it ON.

[0099] The load signal VG is outputted as a predetermined voltagebetween the power source voltage VDD and the ground voltage so that thePMOS transistor MP2 is biased. The PMOS transistor MP2 functions as aconstant current source which is turned ON with a predetermined biasstate. Or it can be regarded that a resistance element having apredetermined ON resistance is connected between the internal powersource voltage VII and the ground voltage. A current depending on thisON resistance flows as a load current.

[0100] The voltage value of the load signal VG can be set appropriatelyby exchanging a transfer gate to be turned ON depending on the loadsetting signals LDS<i:0>. A current value flowing as the virtual loadcan be set up appropriately. Further, if the load setting signalsLDS<i:0> are exchanged dynamically, a load current of the internal powersource voltage VII which changes in actual operation with a time passagecan be reproduced falsely.

[0101] A second specific example of the fourth embodiment of the virtualload section shown in FIG. 15 includes a virtual load section 24B and aload signal generating section 94B. In the virtual load section 24B, theinternal power source voltage VII and resistance element are selectivelyconnected through a transfer gate, so that each transfer gate has aresistance element having a different resistance value. Consequently, adifferent load can be connected depending on a transfer gate to beselected and turned ON.

[0102] The load signal generating section 94B includes a decodingcircuit. The load setting signals LDS<i:0> to be inputted as digitalsignal from the external terminals T46A are decoded. A transfer gate ofthe virtual load section 24B is selected by decoding signal outputtedfrom the decoding circuit.

[0103] Although the first and second specific examples are indicated insuch a condition that the load setting signals LDS<i:0> are inputtedfrom the external terminals T46A, this signal may be generated withinthe semiconductor integrated circuit device.

[0104] The operation waveform shown in FIG. 16 indicates a case whereupon adjustment of the internal power source voltage VII, the internalpower source voltage VII becomes a predetermined value with respect toadjacent paring adjustment signals XAD<1:0>(X indicates “E”, “C”, or “B”here). A high-level judgment signal JG is outputted at continuous twocycles. More specifically, when the adjustment signals (XAD<1>,XAD<0>)=(1, 0) are dispatched, a relation VII=VII0 is attained, so thata lower limit value in a voltage value region of the predetermined valueis reached. Further, when the adjustment signals (XAD<1>, XAD<0>)=(1, 1)are dispatched, a relation of VII=VII1 is attained, so that a upperlimit voltage value in a voltage value region of the predetermined valueis reached. Although FIG. 16 indicates a case where the internal powersource voltage VII becomes a predetermined value at continuous twocycles, there is a possibility that the internal power source voltageVII becomes the predetermined value over three or more cycles.

[0105] In such a case, if it is so set up that the adjustment signalsXAD<1:0> are stored at a first cycle when the judgment signal JG becomesa high level, an accurate adjustment signals XAD<1:0> can be stored evenwhen the judgment signal JG continues to be a high level over pluralcycles.

[0106] As described above, according to the semiconductor integratedcircuit device of this embodiment and the adjustment method of thesemiconductor integrated circuit device, the semiconductor integratedcircuit device includes the judgment section 1, 11 and the judgment stepis carried out within the semiconductor integrated circuit device. Foreach of the adjustment signals XAD<m:0>(X indicates “E”, “C”, or “B”),the internal power source voltage VII which is an analog signaloutputted from the internal power source circuit 31, 31A, which is anexample of the analog signal generating section 3, is compared with apredetermined value and judged. Therefore, the judgment on the internalpower source voltage VII can be carried out within the semiconductorintegrated circuit device.

[0107] The internal power source voltage VII does not have to beoutputted to an external terminal of the semiconductor integratedcircuit device. Thus, the semiconductor integrated circuit device doesnot require provision of an output external terminal of the internalpower source voltage VII or wiring for the internal power source voltageVII to the output external terminal. Consequently, care to designing onanalog wiring is not required, so that designing load of thesemiconductor integrated circuit device can be reduced.

[0108] Because the internal power source voltage VII is not outputtedfrom the external terminal, any test for analog signal is not required.Only a tester device having digital test function needs to be providedfor an external terminal of digital interface. It is not necessary toprovide with any complicated tester device which achieves both digitalfunction and analog function. Further, test condition exchange betweendigital function and analog function is not required, thereby reducingan overhead of the test time which is generated with the test conditionexchange. Consequently, test cost can be reduced.

[0109] The reference voltages VII0, VII1, VII0-VII3 for setting thepredetermined value are analog values and obtained by dividing the powersource voltage VDD supplied from the external terminal T13A through theresistance element array of RC0-RC2, RC0-RC4 provided on the comparators12A, 12B. If the power source voltage VDD is set to the predeterminedvoltage value at the time of adjustment test, any analog value forpredetermined value setting does not need to be inputted from anyspecial external terminal.

[0110] Further, the predetermined value mentioned here refers to thefirst and second comparison reference values. This value is apredetermined voltage value region surrounded by the reference voltagesVII0 and VII1 (in case of FIG. 4) and the reference voltages VII1 andVII2 (in case of FIG. 7). Further, it is possible to judge in whichregion the internal power source voltage VII exists of voltage valueregions partitioned by two or more comparison reference values, that is,the reference voltages VII0 and VII1, VII0 to VII3. Consequently, adifference between the internal power source voltage VII and thepredetermined value can be grasped, so that the adjustment signal can betransferred depending on the judgment signal JG, JG<2:0> and broughtnear the predetermined value rapidly.

[0111] Preferably, the judgment section 1, 11 includes plural comparingsections C0, C1 (in case of FIG. 4) or C0-C3 (in case of FIG. 7) forcomparing the internal power source voltage VII with the referencevoltage and encoding sections 13A, 13B in which comparison signals areinputted from plural comparing sections and which identifies in whichvoltage value region the internal power source voltage exists.Consequently, if the judgment signal JG, JG<2:0>, which is an encodingsignal, includes a digital signal having bit number capable ofidentifying a voltage value region, a judgment result can be expressedwith digital signal of minimum bit number. As for the external terminalfor outputting the judgment signal JG, a minimum number of thoseterminals only has to be secured.

[0112] Storage of the predetermined signals FS<m:0> into a fuse circuit(or memory circuit) 41, 41A having fuse elements or memory elements,which act as a predetermined signal storing section, can be carried outindependently under an external control such as a tester device. After asequence of test based on the tester device is completed, the storageoperation can be carried out.

[0113] If the predetermined signal storing section is constituted ofmemory circuits (fuse circuits) 42, 42A, 43, 43A, by generating thecontrol signal within the semiconductor integrated circuit device basedon the judgment signal JG, the writing of the adjustment signalsCAD<m:0>, BAD<m:0> into the memory elements can be executed. Further, byproviding the semiconductor integrated circuit device with a circuitstructure for cutting off fuse elements electrically, the fuse elementscan be cut out depending on the adjustment signals CAD<m:0>, BAD<m:0>based on the judgment signal JG.

[0114] The memory elements may be constituted of volatile memory cellsused for SRAM, DRAM or the like, like the memory circuit 42A. Further,the memory elements may be constituted of nonvolatile memory cellselectrically rewritable, provided on a flush memory or the like, likethe memory circuit 43, 43A. Additionally, this function may be achievedby a circuit structure having data holding function such as a register,flip-flop instead of the memory cell.

[0115] Further, because virtual load step is executed under provision ofthe virtual load sections 24A, 24B, virtual load can be connectedappropriately when the internal power source voltage VII is adjusted.Various kinds of operation conditions in the semiconductor integratedcircuit device such as digital function, other analog function can bereproduced falsely. Consequently, the internal power source voltage VIIcan be adjusted under a load condition near the actual operation.

[0116] In the meantime, the present invention is not restricted to theabove-described embodiments, but needless to say, may be improved ormodified in various ways within a scope not departing from the gist ofthe present invention.

[0117] For example, although under these embodiments, the internal powersource circuit is taken as an example of the analog signal generatingsection and a case where the internal power source voltage VII isadjusted as the analog signal has been described, the present inventionis not restricted to this example. Additionally, the present inventionmay be applied to a case in which a necessity of adjusting other analogvalues such as bias voltage, bias current exists.

[0118] In this case, the virtual load section may be so constructed toconnect a current source as a load or to connect an impedance element ona power source or an analog signal path.

[0119] Although as the fourth embodiment, a case where the PMOStransistor or a resistance element is connected as the virtual loadsection, the present invention is not restricted to this example.Needless to say, the virtual load section may be constituted of the NMOStransistor, a junction FET, bipolar transistor, diode, capacitor or thelike, or other active element or passive element or an appropriatecombination of these elements.

[0120] According to the semiconductor integrated circuit device and theadjustment method of the same semiconductor integrated circuit device ofthe present invention, when analog signal outputted from the analogsignal generating section such as an internal power source circuitincorporated in the semiconductor integrated circuit device is adjusted,a result of comparison and judgment between the analog signal and apredetermined value does not need be outputted through an externalterminal outside the semiconductor integrated circuit device. Further,the result of comparison and judgment may be converted to digital signaland outputted through the external terminal. That is, an external testerdevice and test method can be simplified so that the adjustment test canbe carried out accurately and rapidly. Further, a pseudo load can beconnected to an analog signal depending on load setting signal andtherefore, the analog signal can be adjusted under a similar loadcondition to the actual operation of the semiconductor integratedcircuit device.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: an analog signal generating section for outputting an analogsignal; and a predetermined signal storing section for storing at leastone predetermined signal that is supplied to the analog signalgenerating section and sets the analog signal to a predetermined value,wherein digital signals are used for input/output interface to externalterminals, for adjusting the analog signal, the semiconductor integratedcircuit device further comprises a judgment section for outputting atleast one judgment signal that corresponds to a comparison result of theanalog signal corresponding to at least one adjustment signal and thepredetermined value generated based on power source voltage, for eachadjustment signal supplied to the analog signal generating section inaccordance with a test signal, and in case the judgment signal judgesthat the analog signal has the predetermined value, the adjustmentsignal corresponding to the as-judged analog signal is stored in thepredetermined signal storing section as the predetermined signal.
 2. Asemiconductor integrated circuit device according to claim 1 furthercomprising a signal selecting section that is controlled by the testsignal and supplies either the adjustment signal or the predeterminedsignal to the analog signal generating section.
 3. A semiconductorintegrated circuit device according to claim 1, wherein the adjustmentor the predetermined signal is digital signals of two or more than twobits and inputted to a decoding section arranged at a preceding stage ofthe analog signal generating section.
 4. A semiconductor integratedcircuit device according to claim 1, wherein the predetermined value isa predetermined analog value region between a first comparison referencevalue and a second comparison reference value, and the judgment signaljudges which analog value region sectioned by two or more comparisonreference values including the first and the second comparison referencevalues the analog signal exists in.
 5. A semiconductor integratedcircuit device according to claim 4, wherein the judgment sectionincludes: a plurality of comparing sections for comparing the analogsignal with each of the two or more comparison reference values; and anencoding section for outputting encoding signals in a manner ofreceiving output signals from the plurality of comparing sections anddiscriminating the analog value region where the analog signal exists.6. A semiconductor integrated circuit device according to claim 4,wherein the two or more comparison reference values are obtained bylowering/dividing power source voltage.
 7. A semiconductor integratedcircuit device according to claim 1, wherein the analog signalgenerating section is an internal power source voltage generatingsection and outputs internal power source voltage as the analog signal.8. A semiconductor integrated circuit device according to claim 1,wherein the predetermined signal storing section includes memoryelements or fuse elements, and the predetermined signal storing sectionis controlled inside the semiconductor integrated circuit device basedon the judgment signal for data-write on the memory elements or cuttingout the fuse elements.
 9. A semiconductor integrated circuit deviceaccording to claim 1, wherein the judgment signal is a digital signaland outputted from the external terminal.
 10. A semiconductor integratedcircuit device according to claim 1, wherein the predetermined signalstoring section includes fuse elements or memory elements, and based onexternal control to the judgment signal outputted, data-write on thememory elements or cutting out of the fuse elements is conducted.
 11. Asemiconductor integrated circuit device according to claim 1 furthercomprising an adjustment signal generating section for outputting theadjustment signal in order under activation control by the test signal.12. A semiconductor integrated circuit device according to claim 11,wherein the adjustment signal generating section includes an oscillationsection for outputting an oscillation signal having predeterminedfrequency, and counter section for counting the oscillation signal,transitioning and outputting the adjustment signal with constant cyclebased on the predetermined frequency.
 13. A semiconductor integratedcircuit device according to claim 1 further comprising a self-diagnosistest circuit for executing predetermined tests for the predeterminedinternal circuits inside the semiconductor integrated circuit device,wherein adjustment test of the analog signal is executed as one of testsby the self-diagnosis test circuits.
 14. A semiconductor integratedcircuit device according to claim 13, wherein the test signal, theadjustment signal, and the judgment signal are inputted to/outputtedfrom the self-diagnosis test circuit.
 15. A semiconductor integratedcircuit device comprising: an analog signal generating section foroutputting an analog signal; and a predetermined signal storing sectionfor storing at least one predetermined signal that is supplied to theanalog signal generating section and sets the analog signal to apredetermined value, wherein digital signals are used for input/outputinterface to external terminals, and the semiconductor integratedcircuit device further comprises virtual load section for varying loadagainst the analog signal in response to a load setting signal to besupplied.
 16. A semiconductor integrated circuit device according toclaim 15, wherein the analog signal generating section is an internalpower source voltage generating section and outputs internal powersource voltage as the analog signal, and the load is a current sourcecircuit for generating load current.
 17. An adjustment method of asemiconductor integrated circuit device that generates an analog signalhaving a predetermined value based on at least one predetermined signalstored and uses digital signals for input/output interface to externalterminals, for adjusting the analog signal, the adjustment methodcomprising the steps of: a signal generating step for generating theanalog signal that corresponds to at least one adjustment signal; ajudgment step for judging a comparison result of the analog signalgenerated and the predetermined value generated based on power sourcevoltage, the judgment step being executed inside the semiconductorintegrated circuit device; and a storing step for storing the adjustmentsignal as the predetermined signal in case the analog signal is judgedas having the predetermined value through the judgment step.
 18. Anadjustment method of a semiconductor integrated circuit device accordingto claim 17, wherein the adjustment signal makes stepwise transition andthe signal generating step and the judgment step are repeated for eachadjustment signal.
 19. An adjustment method of a semiconductorintegrated circuit device according to claim 17, wherein the storingstep is executed inside the semiconductor integrated circuit device. 20.An adjustment method of a semiconductor integrated circuit deviceaccording to claim 17, wherein judgment of the comparison result isoutputted from at least one of the external terminals in a form of atleast one digital signal.
 21. An adjustment method of a semiconductorintegrated circuit device according to claim 20, wherein the storingstep is controlled outside the semiconductor integrated circuit device.22. An adjustment method of a semiconductor integrated circuit deviceaccording to claim 21, wherein the storing step includes: a signalobtaining step for obtaining the adjustment signal as the predeterminedsignal in case the analog signal is judged as having the predeterminedvalue; and a write step for writing the obtained predetermined signal ina predetermined signal storing section.
 23. An adjustment method of asemiconductor integrated circuit device that generates an analog signalhaving a predetermined value based on at least one predetermined signalstored and uses digital signals for input/output interface to externalterminals, the adjustment method adjusting the analog signal through avirtual load step for varying load against the analog signal inaccordance with a load setting signal.